1 radiation hardened high speed, quad spst, cmos analog switch hs-201hsrh, hs-201hseh the hs-201hsrh, hs-201hseh are monolithic cmos analog switch featuring power-off high input impedance, very fast switching speeds and low on-resistance. fabrication on our di rsg process assures sel immunity and only very slight sensitivity to low dose rate (e ldrs). these class v/q devices are tested and guaranteed for 300krad (si) total dose performance. power-off high input impedance enables the use of this device in redundant circuits without causing data bus signal degradation. esd protection, overvoltage protection, fast switching times, low on-resistance, and guaranteed radiation hardness, make the hs-201hsrh ideal for any space application where improved switching performance is required. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed below must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-99618 . a ?hot-link? is provided on our homepage for downloading. features ? electrically screened to dla smd# 5962-99618 ? qml qualified per mil-prf-38535 ? radiation performance - high dose rate (50-300rad(si)/s). . . . . . . . . . . 300krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . . 50krad(si) - sel immune . . . . . . . . . . . . . . . . . . . . . . . . . di rsg process ? overvoltage protection (power on, switch off) . . . . . . . . . . . 30v ? power off high impedance . . . . . . . . . . . . . . . . . . . . . . . . 17v ? fast switching times -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110ns (max) -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80ns (max) ? low ?on? resistance . . . . . . . . . . . . . . . . . . . . . . . . 50 (max) ? pin compatible with industry standard 201 types ? operating supply range . . . . . . . . . . . . . . . . . . . . . . .10v to 15v ? wide analog voltage range ( 15v supplies) . . . . . . . . . . . . 15v ? ttl compatible applications ? high speed multiplexing ? sample and hold circuits ? digital filters ? operational amplifier gain switching networks integrator reset circuits pin configuration hs1-201hsrh, hs1-201hseh sbdip (cdip2-t16) hs9-201hsrh, hs9-201hseh flatpack (cdfp4-f16) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a1 out1 in1 v- gnd in4 a4 out4 a2 in2 v+ nc in3 out3 a3 out2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2000, 2006, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. june 24, 2013 fn4874.2
hs-201hsrh, hs-201hseh 2 fn4874.2 june 24, 2013 ordering information ordering smd number (note 3) internal mkt. number (notes 1, 2) part marking temp. range (c) package (rohs compliant) pkg. dwg. # 5962f9961801vec hs1-201hsrh-q q 5962f99 61801vec -55 to +125 16 ld sbdip d16.3 5962f9961802vec hs1-201hseh-q q 5962f99 61802vec -55 to +125 16 ld sbdip d16.3 5962f9961801qec hs1-201hsrh-8 q 5962f99 61801qec -55 to +125 16 ld sbdip d16.3 5962f9961801vxc hs9-201hsrh-q q 5962f99 61801vxc -55 to +125 16 ld flatpack k16.a 5962f9961802vxc hs9-201hseh-q q 5962f99 61802vxc -55 to +125 16 ld flatpack k16.a 5962f9961801qxc hs9-201hsrh-8 q 5962f99 61801qxc -55 to +125 16 ld flatpack k16.a 5962f9961801v9a hs0-201hsrh-q -55 to +125 die 5962F9961802V9A hs0-201hseh-q -55 to +125 die hs1-201hsrh/proto hs1-201hsrh/proto hs1-20 1hsrh/proto -55 to +125 16 ld sbdip d16.3 hs9-201hsrh/proto hs9-201hsrh/proto hs9-201hsrh/proto -55 to +125 16 ld flatpack k16.a hs0-201hsrh/sample hs0-201hsrh/sample -55 to +125 die note: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for hs-201hsrh , hs-201hseh . for more information on msl, please see tech brief tb363 . 3. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table on page 2 must be used when ordering
hs-201hsrh, hs-201hseh 3 fn4874.2 june 24, 2013 die characteristics die dimensions 2790m x 4950m (110 mils x 195 mils) thickness: 483m 25.4m (19 mils 1 mil) interface materials glassivation type: phosphorus silicon glass (psg) thickness: 8.0k ? 1.0k ? metallization type: ti/alcu thickness: 16.0k ? 2k ? substrate rad hard silicon gate, dielectric isolation backside finish silicon assembly related information substrate potential unbiased (di) additional information worst case current density <2.0 x 10 5 a/cm 2 transistor count 328 metallization mask layout out4 in4 gnd v- in1 a4 a3 a1 a2 out3 in3 v+ in2 out2 out1
hs-201hsrh, hs-201hseh 4 fn4874.2 june 24, 2013 package outline drawing k16.a 16 lead ceramic metal seal flatpack package rev 2, 1/10 side view top view section a-a -d- -c- seating and base plane -h- base lead finish metal pin no. 1 id area 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 bsc) 0.440 (11.18) 0.005 (0.13) min max 0.115 (2.92) 0.045 (1.14) 0.045 (1.14) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) min 0.13 (3.30) min 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 lead finish 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. 8. notes: dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the
hs-201hsrh, hs-201hseh 5 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn4874.2 june 24, 2013 for additional products, see www.intersil.com/product_tree ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d16.3 mil-std-1835 cdip2-t16 (d-2, configuration c) 16 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n16 168 rev. 0 4/94
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